Investigations for 1130 MRAM board - ways to block retriggering of the timer chip

DESIGNING WIDE SCHMIDT TRIGGER CIRCUIT

I see that the noise that shows up on the +Storage Read or +Storage Write line dips from 3V down to just under 2V, which is enough to overcome the Schmidt Triggers in the timer chip. It thus looks like a request to trigger anew. A Schmidt Trigger is a gate with asymmetric on and off voltage levels. It has an upper and a lower threshold voltage, where it switches on only when the input rises above the upper threshold. It won't switch off until the input drops below the lower threshold. 

The thresholds on chips are set for modern signaling levels, such as TTL or LVCMOS 3.3V.  SLT has its own signal levels which are not the same as the modern devices. While I can get away with using LVCMOS 3.3 devices with SLT in most cases, SLT defines logic low at .3V or less and a logic high at 1.8V or higher with full high at 3V. 

The signal causing the problems shoots up to 3V and stays there, but has some noise that dips down to just under 2V briefly. According to SLT, that is a valid high signal and it never went to low. The timer chip devices a logic high as 2V or higher and a logic low as .8V or lower. The dip in the noise is seen as a brief change to logic low and a return to logic high - viewed from the timer chip - but is not an issue for the 1130's SLT logic. 

Texas Instruments datasheet for the SN74LVC1G123 chip states that the inputs have 'sufficient hysteresis to handle slow input transition rates with jitter-free triggering of the outputs.' The intent here is that a very slow signal change may wobble around the turn-on threshold voltage and be seen as many on and off transitions. Their design aims to reduce that risk by having different upper and lower threshold voltages. 

They don't define the threshold voltages specifically but the datasheet recommends minimum logic high inputs of 2V and maximum logic low inputs of 0.8V to work reliably with a 3.3V VCC. The noise on the input dips below the 2V for a very brief time, but sufficient for the timer chip to retrigger because it thinks it went low. The voltage thresholds are not handling this situation. 

I began to whip up a wider range Schmidt Trigger for the inputs, one I would set to turn on when a signal hits 2.4V and to not turn off until it drops to 0.8V. That is a sufficient span to ignore the noise on the input lines. I did this with discrete transistors and the aid of LTSpice to simulate the circuit at full speed (about 277KHz) for the input memory signals. 

Complications abound. The SLT output that drives the +Storage Read and +Storage Write signal uses a germanium transistor with a 750 ohm pullup resistor to +3V. The transistor has only a 0.3V drop due to the properties of Germanium, which is why SLT uses 0.3 as a logic low threshold. Worse, the 750 ohm pullup must be factored into any circuit receiving the signal as the voltage detected on the transistor receiving the signal will be divided down by a resistor in the trigger circuit. 

Thus if I have a trigger circuit with a 100 ohm common emitter resistor, the input voltage seen at the base of the transistor is 100/850th of 3V, or only about .353V which is below the 0.6V diode junction of modern silicon based transistors. I have to bump up the common emitter resistor quite a bit to get a good voltage swing for the incoming signal. This drops the current through the transistors making them a bit slower to switch. 

I worked up a circuit with a common emitter resistor of 1.5K that switches on at 1.85V and switches off a 0.9V. This is not the ideal range I envisioned but enough to work properly with the noise I am experiencing on the input line. The circuit produces an output that swings between 2.4V and 3V which I then have to convert to voltages that will trigger the CMOS input circuitry inside the timer chip. 

I don't have the detailed circuit of the timer chip, but I can model a typical CMOS inverter input and simulate until my design works reliably with the conditions I am experiencing. I am working on that final piece right now. 

I have been doing quite a bit of simulation, experimenting with the characteristics of the flat ribbon cables used in the IBM 1130 to deliver the signal to my PCB. Using the characteristic inductance, capacitance and resistance, I modeled SLT driver and receiver gates and looked for any kind of reflections or noise on the line in different conditions. 

I then modeled with an SLT output gate, the cable, and a CMOS inverter input gate to see if there was bouncing, ringing or other phenomena that might explain my situation. To no avail so far. Ringing or bouncing should happen on the rise or the fall of a signal, not 1 microsecond into a 1.6 uS steady signal. This is asynchronous to what is going on in the IBM 1130 so I have a very hard time believing that it is the cause of this glitching. 

If I have to build the Schmidt Triggers for the two inputs, it will add about thirty small parts to the design and require another expensive round of PCB manufacture. I think I could breadboard the trigger circuit and insert it temporarily just to see if I can bypass the problems. This does feel like a Rube Goldberg fix to a problem. I will be much happier if I can figure out why this is happening and can fix it at the source.