Friday, April 3, 2015

SAC Interface testing and logic improvement


I went out to further test the circuits for Channel Data In bits 0, 5 and 8 which didn't seem to transfer as a 1 when they should. My tests included proper resistance, voltages as measured at both ends of the cable, and voltages on the output side of the SLT card gate. Bit 5 wasn't even bad, it was burned out bulbs on my console display panel. Only real problems are bits 0 and 8.

I discovered that in spite of my beliefs to the contrary, bits 0 and 8 did NOT have proper continuity to the input pins they should. These are the pin D02 of the SLT card for the two cards that span the top and bottom halves of the input register. I see good resistance and get the +2.975 V on the pin on the backplane and my driver board. However, when the driver board pulls that wire down to zero, the voltage at the SLT card pin is still +3V, not low. Something is interrupting the action but I am not sure what at this point.

Ah, for the schematic for the SLT card. Still, I will poke around until I find what is different between D02, the input for bit 0/8 and other input puts such as D04 which represents bits 1/9. Might be a socket problem, a backplane problem, a connector on the backplane or something on the card which is particularly susceptible to failure with time.

Continuity checking definitely shows the driver output in my box is connected to the input pin where the cable enters the SLT backplane and as well to the entry pin on the SLT card. Time for another test, in case I scraped off oxide on the connectors as I reseated everything on the SLT backplane. Otherwise, time to start testing the two cards themselves. It is hard to imagine that the same error occurred on two cards simultaneously, unlikely but not impossible.

Meanwhile, I updated my FSMs for the other XIO functions and for cycle steal, now that I have reliable mirroring of the clock rings and XIO E phases. As usual, I reached a point where I was fighting with the Xilinx toolchain for quite a while since it was stubbornly refusing to notice that I had changed the signal list in a submodule and its instantiation in my main module - keeping the old definition somewhere.

I decided to set up buttons to trigger cycle steal read and write, in order to test out those functions. Cycle steal will be the first time I try out the other two SLT cards, those that receive the Channel Address In register signals.

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