Friday, February 20, 2015

Put 1442 together, found issues with SAC Interface box, plus small tasks


I lubricated the card feed clutch as I assembled it, then put it all together. I hand cranked it through a feed cycle and found that the mechanism hangs up when it is about 330 degrees around the cycle, bumping into some part of the clutch release mechanism which has to be tripped again to get the machine back to its 0 degree rest spot.

At this point, the reader is ready to be adjusted and tested some more. The feed clutch adjustments definitely have changed and need work, but it would be a very good idea to methodically adjust the machine from beginning to end. We found with the 1402 reader/punch on the 1401 systems at Computer History Museum, that only a complete sequenced set of adjustments would do away with the sporadic read checks and other problems that had been plaguing the systems for many months.

I closed it up to work on some other items first, but expect it won't be long before I am adjusting and testing this again. I have the manuals and appropriate tools to let me work my way through the adjustment process.


An enthusiast is using the programs and data that make music over a radio on an 1130, but converting them to another purpose. He spotted some apparent garbage in the deck of songs data, which lead me to re-read the deck and verify it with a second pass to compare the hole patterns.

However, there are still some suspect results, so I went to the ultimate source - the physical cards - and took a look at the line in question. Indeed, it was mis-read, twice the same way unfortunately so that it passed verification.

I will hand-annotate the file with the intended values from the cards then re-post it. Hopefully that will produce better results for the 1130 enthusiast. I found errors on one card from the initial reading but the corrected card is in the version I read then verified. The cards in question from that file all compared exactly to the physical cards in my hand.


I am still debugging the viability of the existing FMC Carrier S6 fpga board - trying to change enough to validate that it is working correctly. At this point, I see some life from the fpga when I directly load the bitstream, but it is not able to find and boot from its ROM when powered up.

My blinking light routine is displaying signs of life and I also see the reset button (BTND) working correctly. However, none of my lights on the expansion board or the set of 16 wired to other pins on the board are lighting.

Further, I still see severe delays on input signals from the 1130 appearing as outputs of my bus receiver circuit. Not sure if these are related, but the lack of operation of the LEDs that had been working when first constructed suggests some problem that might also be fighting input swings.

I am going to temporarily move one of the signal from the fpga and wire it to a TTL load, then scope the behavior of my receiver circuit. If the delay goes away, I can focus solely on diagnosing the fpga board. If, however, I still have almost 300ns of delay, most of a T cycle, then I need to redesign the interface electronics.

Before I did the test, I pulled up the spec sheet on my 2N3904 transistors used in the circuit and discovered to my horror that the transistor has a shutoff time of 240ns, exactly what I am seeing. These are inverted logic levels coming from the 1130 thus when the T6 cycle line is activated, the incoming voltage drops, cutting off the bias to the 2N3904 and the transistor should cut off, popping the output signal up to 3.3V. Which it does, including the 240ns delay to switch off. Yikes.

The problem is storage time of the transistor - since my circuit puts it into saturation when it is conducting, the charge has to diffuse away which is a slow process. If the circuit keeps the transistor out of saturation and barely operating, so that there is less charge to eliminate, making it switch off faster. A capacitor across the base bias transistor can remove the charge faster as well.

I will have to modify my receiver circuit or select a transistor with a much faster shutoff characteristic, breadboard it and wire it into the T6 signal path to observe its behavior. If it works as it should, I can lay out and build the 77 circuits necessary to replace my failed first attempt.

You can tell from this that I am new to electronics design, not even thinking about asymmetric transistor behavior or specifications that the circuit must meet. Once bitten, I will think about this for future designs, as an experienced electronics hobbyist probably would have. Sadly, the simulator web site I used to test the design wasn't giving me realistic timing, just voltage swings. I tested to see that it meet the voltage margins and logic level commitments, but not the speed of operation.

I still have issues with the fpga board plus extender - no lights and the inability to get it to correctly boot at power up from a ROM stored bitstream. I will do some debugging but now that I know the interface boards have to be replaced anyway, there isn't much time to be saved by preserving the cabling and pin assignments I made. Thus, the 'cost' to me of switching to a new fpga board isn't high.

I therefore just bought a ZTEX 2.01 board, which should arrive in 2-3 weeks. Even with shipping from Germany and a paypal surcharge, it was under $120 for the board. In the interim I will get the receiver and driver circuits behaving correctly.


I added some Silicone sealant around the outdoor outlet box on the side of my house, as a belt and suspenders oriented safety margin in case water somehow enters the outdoor rated box. 

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