Thursday, May 12, 2022

Assessing more of the functionality of the 1130 processor; looking good so far


The IBM 1130 is built around core storage, thus instruction processing involves some number of storage cycles. Each storage cycle has a designation depending on its purpose in either preparing the instruction for execution or actually implementing the operation. 

The first fetch of a word for a new instruction is I1. This reads the word at the location pointed to by the Instruction Address Register (IAR) into the Storage Buffer Register (SBR) by transferring the IAR to the Storage Address Register (SAR) at the start of the cycle. 

IBM 1130 instructions can be short or long, that is they can take one or two words of memory. Bits in an word are numbered from left to right as 0 through 15. Bits 0, 1, 2, 3, and 4 are the op code for an instruction. Bit 5 set to 1 makes this a long instruction. 

For long instructions, the next storage cycle is I2, which fetches the next sequential word as the second part of the instruction. Generally this is the address that the instruction will use for its operand. 

The 1130 supports indirect addressing, indicated by bit 8 set on in the first word. This means that the contents of memory fetched in storage cycle I2 are an address that is then read in a further storage cycle IA to pick up the operand value. Long instructions that are not indirect use the contents of the second word, indirect instructions use the second word as an address and fetch from that address for the contents. 

Another addressing functionality of the 1130 is the use of index registers. If bits 6 and 7 are non-zero, they select index registers 1, 2 or 3 that are used to further modify the contents we picked up with cycles I1, I2 and IA. Short instructions use the next sequential address from the IAR as their content, long instructions use the content of the next sequential address from the IAR, and indirect instructions use the contents of the address picked up from the next sequential address from the IAR. 

The IX storage cycle grabs the value of the index register being used, if a non-zero value is in instruction bits 6 and 7. The 1130 stores the index registers in fixed locations in memory - locations 0001, 0002 and 0003 respectively. Thus we have a fetch of the contents of one of these three words during an IX cycle.

Finally, the contents selected by I1, I2 and IA cycles has the contents of the index register selected in IX added to it, the resulting value is the effective address or operand address. 

I wanted to check all the combinations of short, long, indirect and indexed addressing to be sure that the machine selected the proper storage cycles to take among the I1, I2, IA, and IX options. I checked that for each storage cycle it put the proper number in the SAR, e.g. for an index register 0001, 0002 or 0003 is put into the SAR at the start of that cycle. I validated that the computed effective address was correct.


When an instruction has been prepared, with the effective address determined and its operation code and flag bits saved, it is time to actually execute the instruction. This takes one or more execution cycles, E1, E2 and E3, with only certain input-output instructions requiring all three. 

The 1130 is a register oriented machine which means that instructions either act only on a register or act on a register and one storage location. The instructions that store a result use the execution cycle to place the appropriate value in the effective address in core. The instructions that use storage as one argument, for exampling adding a value from storage to the current value of a register, use the E cycle to fetch the data and then accomplish the function such as addition near the end of the storage cycle. 

I tested out load, addition, shift-rotate and conditional branch instructions to verify that they produced the proper output. This was not an exhaustive test of every instruction and every edge case per instruction, just a reasonable sample to assess how solid the processor logic appeared to be. 

Some instructions need more than the eight 450ns clock pulses per storage cycle that is standard in the machine. Therefore, when the T-clock advances from T0 to T7 it has to stay there and take additional T7 cycles until the task is complete. One example of this is shifting - bits are shifted one position per 450ns clock pulse thus for a longer shift we would need to stay in T7 until we were through. 

The counting for tasks like shifting, multiply and divide are done by a Cycle Control Counter (CCC) that has to reach 0 before we stop taking T7 and move on to T0 of the next storage cycle. This gets verified with the shift instruction tests.

Adding or subtracting in the 1130 requires multiple 450ns cycles to accomplish. The value of the operand fetched during E1 storage cycle is put in the Arithmetic Factor Register (AFR) and then the ACC and AFR do rounds of addition or subtraction (or logical AND, OR or XOR depending on the instruction) 

For each 450ns round, the corresponding bit positions of AFR and ACC are added, producing a result value in the ACC bit location and if there is a carry or borrow, it is put in the AFR bit position one to the left. I will use an example to illustrate this, with two values in the AFR and ACC then the result after a round of addition:

    AFR    0100 0011 0101 1011

    ACC    0000 0001 1000 0010

        after one round

    AFR    0000 0010 0000 0100

    ACC    0100 0010 1101 1001

        second round produces below results

    AFR    0000 0100 0000 0000

    ACC    0100 0000 1101 1101

        third round see below

    AFR    0000 0000 0000 0000

    ACC    0100 0100 1101 1101

Once the AFR is all zeroes, the machine stops taking additional T7 cycles and the addition is complete. We see that we added x435B to x0182 and produced the proper result x44DD but it took several rounds to handle all the carry situations. 

I verified that this worked properly, taking individual 450ns cycles (Single Step mode). I also checked that the Carry and Overflow indicators were set when they should be. 

The shift test involved rotation of bits out of the right end of ACC and into the left end of EXT. I also attempted some input-output to the keyboard and console entry switches.


All of the instructions I issued, in all the addressing modes, worked properly. In fact, I discovered that my issue from yesterday where I thought the Rotate shift instruction wasn't moving bits to the EXT was in fact user error. I miscoded the instruction and had a simple shift right 10. When I did it correctly the machine worked properly.

Conditional branch instructions, arithmetic, whatever I threw at the machine seemed to work properly. In all my testing today I was only able to discover two items that need work. One was inability to read from the keyboard and the other was sporadic parity errors. 

Issuing a Control command via the XIO (execute IO) instruction should trigger the solenoid to unlock the keyboard for input, but it didn't respond. I was able to successfully read the 16 toggle switches of the Console Entry Switch, so this is something specific to the keyboard and its controller cards. 

The parity errors crop up on reading a word, in most cases it was bit 0, the high bit, that came on when it should have been 0. The machine will run fine with the Storage Display CE switch, but sometimes when executing instructions I see the parity error. Once it reports the error the word is indeed corrupted in storage as it trips repeatedly at that location. 


The rotary mode switch gets a lot of use when sitting at the machine testing - selecting various single step, single storage cycle or single instruction, loading and displaying, then normal Run mode are frequent actions. 

The switch was very crunchy and hard to turn. From time to time it would jam up and need some persuasion to rotate again. I suspect that the bearings are gummed up or damaged, however there is no lubrication opening. 

I happened to own a real 1130 rotary mode switch, something I had built into my IBM 1130 replica computer. I grabbed that and soldered it in place of the bad switch. This let me continue with my debugging but ultimately I will either disassemble and repair the bad switch or find a different replacement for it.  

Swapping rotary switches

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