NEW, IMPROVED CIRCUIT DIAGRAM
I also have not drawn the full dot-OR from the Run flipflop, actually an MGTR SLT module, which includes an input from the Program Load circuitry and a loop back to the gates that set and reset this flipflop.
Everything else is specified with the pin numbers of the SLT modules listed. You can see two AND circuits, one in the left of the AOXb module and one in the left of the AOI module. These have a pullup resistor to +6V and diodes that will only pull that junction down towards 0 if the input is low otherwise it is in the logic high level.
If the two inputs to the AND circuit are both high, the output is high. If either or both is low, the output goes low. These two AND circuits are passed on through a diode to the OR junction of the AOI at pin 1. These have diodes that will block the flow if the junctions are low but will pass on a logic high voltage onward towards the base of the inverter transistor.
This means that the inverter transistor is switched on if either or both of the AND gates have a logic high output. Since each of these is high only if both of their inputs is high, it means that if either AND gate has both inputs high, the inverter is switched on and goes to a logic low level for its output.
The final step is the high power driver module which inverts again and drives high current to feed many inputs simultaneously - for all the gates or flipflops whose state must be set to a known configuration when the D07 (-DC Reset) signal is low.
We do NOT have a reset when the output of the HPD is high. This means we do not have a reset condition when the output of the OR gate is low. The OR gate output is low when either or both of the AND gates is high. Each AND gate is high when both of its inputs is high.
Unwinding this logically, we see that when the -Power On Reset signal is low, since it goes to both AND gates, neither is on, the OR is therefore high and the HPD output is low; a reset condition is transmitted throughout the 1130.
Also we can see that after the initial power up reset, the -Power On Reset signal is always high and therefore the output of each of the two AND gates is the same as their other input. If -Reset is high, then that associated AND gate output is high. If +Run/Prog Load Dot on Run is high, then that associated AND gate output is high.
We can only get a high output from the OR gate if both of the AND gates are low - either high will pass through and cause -DC Reset to stay high. Effectively, outside of the power up time initialization, we have to have the Reset key pressed at a time when Run is not active. That is, -Reset must be low and +Run/Prog Load Dot on Run must be low.
This may seem an unnecessary complication for the Reset button but it is essential to protect the state of the core memory. A storage cycle consists of eight clock steps, T0 to T7 or X0 to X7, during which the contents of a word of memory are first destroyed to read their prior contents and then (re)written to store their new(old) contents.
If the reset took place before the write was complete but after the word was being destructively read, the contents would be lost. They would not pass parity checking either thus reading the word would bring the 1130 to a halt with a Parity Error condition.
By adding the condition that we are stopped (Run is off), we will not be in the midst of a destructive read followed by write and a reset will not impact any core memory location.
WHERE WE MIGHT HAVE THE ROOT CAUSE OF THE RESET KEY OSCILLATION
Looking at the diagram we see that there are only four diodes, three resistors, one capacitor or possible sneak paths through the other pins on the AOXb module that are not associated with our DC Reset circuit. It shouldn't take that long to investigate these and draw some conclusions. Repairs will depend upon what is faulty and the ease or difficulty of a correction.