GATHERING AT LEAST ONE DESTINATION ON CARD FOR EACH INPUT-OUTPUT
I didn't want to leave the reverse engineering of card 6213 until I had at least each signal coming in to the card and going out of the card traced to at least one component pin on the card. In many cases I could work out the circuit and other components by recognizing design patterns.
I used the continuity checker and spent 30 minutes making sure that I achieved this minimum goal for all the I/O pins on the card. As part of the process I uncovered some non-obvious circuits but in many cases I would find something I recognized and from that guess which other signals were on adjacent pins.
ALWAYS A SURPRISE UNDER THE COVERS
IBM uses edge-triggered logic in many places, although a modern reader would be mislead into believing this is a clock edge triggered gate such as a master-slave flipflop in contemporary components. That is not how this works on the SLT machines such as S/360 and 1130.
Edge triggering generates a short pulse when an edge occurs as long as a gating signal is in the proper state (low). On the oscilloscope I saw generated pulses that were 70ns long. If that short pulse heads to one of IBMs flipflop components the duration is long enough to latch it to the desired state through its 'DC Reset' pins.
Other times, IBM makes use of a Single Shot to generate a known duration pulse, triggered by the less well controlled pulse length out of the edge detector.
Most edge triggered gates are implemented by a junction of a resistor and a capacitor, the resistor hooked to a signal gating whether this is sensitized, a capacitor connected to the signal whose falling edge will cause the pulse and the node wired onward to a logic gate of some sort that receives the pulse. When the trigger is normally at 3V and the gate is set to 0, the falling edge of the trigger signal will produce the pulse. If the gate is at 3V, then the falling edge does nothing.
In most cases IBM draws the ALD as if there were a full And-Invert or And-Or-Invert gate, but the reality is just the resistor and capacitor arrangement in a part or a whole RC module.
|Example of edge triggered 'and' gate|
TESTED LED PLAN FOR RELAY COILS
Other than a technical issue with the reverse voltage across the LED, brought to my attention by a reader, the LED was tested on the 24VAC sequencing power and lights adequately. I added a diode to ensure that only DC is present across the LED.
SMALL COMPLICATION IN WIRING UP THE LEDS
I had hoped to just wire to the relay coil terminals but these are side tabs with the wire soldered on, making an attachment inconvenient. Plan B for the LED showing R1 activation, indicating that all three rails are good, was to locate this on the SMS card where the power is sourced to turn on that relay.
|LED at lower left|
There was not as clean a solution for relay R2, which is the one that passes the +12 and +48 once the machine has completed its power up of the main rails. I hooked it up temporarily just to verify that R2 is not activating, even though relay R1 is switched on.
WIRING ISSUES IN THE POWER SEQUENCE BOX
The contacts on R1 work well, the relay turns on yet relay R2 did not get energized. I did some beeping out with the VOM and found several connections that are not intact. There is a loose wire near R1 and even more troubling, the connection that should power down the machine and lock out the power switch was not working. I wondered why I didn't see it engage that hold relay.
|at least one missing connection|
I am at the point where I can't trust that the wiring for power sequencing is correct. I will have to methodically test every connection and rewire where necessary. Good power is an essential foundation for debugging any complex computer.
IBM wiring diagrams are almost always technically accurate but are often less than helpful to understand a circuit. Below is my redrawing of all the power sequence circuitry where you can follow it to see how it works together. After that I included the three diagrams this is spread across, where you can see that it is much less obvious how the sequencing works.
|My version of the sequencing wiring|
|Main power sequencing diagram|
|More included here|
The most obscure parts in my view are 1) figuring out when R2 and R3 are activated, and 2) seeing the circuit that holds the machine off if it was powered up when all three power rails weren't good. Noticing where the +Power On Reset signal is generated during power sequencing is also a challenge since it is on a different diagram entirely.