Back in workshop and narrowing in on memory parity issue

STEROID INJECTION ALLOWED ME TO WALK AND DRIVE AGAIN

By the weekend I could walk and put weight on my leg again. The swelling was down quite a bit and I am starting physical therapy to restore full extension of the knee to a straight position. This will take away time during the week when from my workshop efforts but is necessary.

PARITY ISSUE CONNECTED TO BIT 7

When I put the 1130 into its Storage Load function using the Customer Engineer switches and set up a bit pattern of 0000, it loops through memory storing that pattern. The Storage Buffer Register should display 0000 continuously during this operation.

However, I see the bit 7 light flickering on when I set the machine to ignore parity errors and keep running. If not, it stops with the first case of bit 7 set on, with the Parity Error lamp lit. The issue is that bit 7 is a 1 sometimes, either because we are not writing the zero properly or because something goes wrong during the read of the word. 

SCOPE WATCHING SIGNALS NARROWS IT DOWN TO SENSE STAGE

I hooked up a scope with lines on the Strobe, Inhibit bit 7 input and the two differential wires that are connected to the two ends of the sense/inhibit wire through the cores. I wanted to see if the inhibit was not being triggered, thus allowing the write cycle to flip the core to the 1 state. It was always present. Further, the differential wires showed the inhibit pulse being fired through the cores. Thus I concluded that the issue I was seeing stemmed from a erroneously detected 1 bit because the core flipped during the read cycle. 

WHY I CAME TO THE CONCLUSION - CORE MEMORY REVIEW

Core memory works by flipping a ferrite core to one of two magnetic orientations, depending on the direction of the current through the X and Y grid wires that suspend the core. The current in any one wire is inadequate to cause the core to flip to the other orientation; it is only when current on two wires that both cross through the core coincide. This is why the method is called coincident current core memory.

A plane with the X and Y wires, having cores at each intersection, provides addressability to any single core and holds 1 bit in each core. To form a collection of bits, such as a 16 bit word of memory, requires a stack of these planes, one per bit of the word being stored. The same X and Y wire has current flowing in all the planes, so that the X and Y address selects that one word - a bit per plane. 

In addition to the two wires running at right angles through the cores - X and Y - there is a third wire that is snaked at a 45 degree angle through many of the cores in the plane. For engineering reasons, the 1130 core memory has a wire for each 2K cores in the plane - two wires in total per plan. This is the wire that provides for both inhibit and sense operations.

Core memory always involves two cycles - read and write - because the process of detecting the state of a core requires you to erase it first. The value just read must be rewritten in the second cycle, or replaced with a new value to be stored. 

The X and Y currents flow through the core to flip its magnetic orientation to the 0 direction. If the core was previously in the same direction, nothing occurs. However, if the core had been magnetized to the 1 direction, the reversal of the magnetic field induces a small current on the sense wire. This is detected by the sense circuit and identifies the contents of that core to have been a 1. No current signifies that the core had been a 0.

The write cycle sends the X and Y current in the opposite direction, to flip the core orientation to the 1 direction. Current in the X or in the Y wire alone is not enough to flip the cores the wire is threaded through, but where the cross the currents combine to cross the threshold. However, if an opposite current is flowing through the sense/inhibit wire, that cancels out some of the current so that the core does not see enough current to flip to 1. This is how we write a 0 into core - by inhibiting the core during the write. 

In order for our core to have bit 7 show up as a 1 sporadically, we need to either write it as 1 or mis-read it as 1. If the inhibit current is working then we conclude we are not writing a 1 to the core. That points us at the read cycle where the cores are flipped to the 0 direction and we detect a pulse from any core that was previously set to 1. 

SCOPE TRACE OF SENSE SHOWS ANOMALY ON BIT 7

I set up the scope to track the Strobe signal, the sense output for bit 7 and the two differential wires that connect to the sense/inhibit wire in the bit 7 core plane. I could clearly see that the differential signal had no activity, indicating that the core was NOT set to 1 prior to the read. However, I saw a pulse emitted on the sense out line indicating the detection of a 1. If I changed the write pattern to make bit 7 a 1, the inhibit differential current was gone and the sense differential current appeared, just as expected. 

Yel - strobe, Grn - sense, Pur/Blu - differential

I monitored some other bits to compared the traces. The differential wires were very clear in showing whether a 0 or a 1 was present at the time of the read. Interestingly, the sense output wires for the other bits did not show a voltage in either case, 1 or 0 value, but the bit 7 always showed a pulse at the time of the strobe pulse(read). 

SWAPPED BOARD FOR SETTING AND READING BIT 7 BUT ERROR CONTINUED

I swapped the board in B3 that handles bit 7 with the board in B7 which handles bit 0, but the same error arose. If that board were defective the error would have moved to bit 0, but it did not. 

Sense/inhibit card

TRIED TO SWAP A7 AND A3 CARDS BUT DAMAGED ONE DUE TO CORRODED GUIDES

The A3 and B3 cards cover the two 4K halves of the core memory, with their sense output wires tied together to produce the single bit 7 output back to the rest of the 1130 circuitry. Thus, a defect on the A3 card might be causing the failure I am reading from the B3 card output pin. I wanted a quick swap to see if moving the A3 down to the A7 position moved the failure to bit 0.

The bottom cards were very hard to remove and insert. The metal guides on the backplane that the SLT card plastic guides slide over had corroded a bit and was thick. This made the card very hard to slide in and out. In trying to pull one of the cards, I inadvertently put pressure on a capacitor on the SLT board which snapped off and fell into the fan assembly. 

Oval shows missing part

I first have to repair the card. I do have a spare card of the same type in my spares/parts box, but I am not certain whether it works properly. I will thus try to repair the original card first. 

POSSIBILITIES

I may be that card A3 is defective. However, it could also be an issue with traces on the backplane serving A3/B3 or circuit continuity out of the core memory compartment over to where the sense pulse is latched in to the B register. Once the card above is repaired and I do the quick swap test I will begin debugging the path to the B register card and find out why the scope pattern is very different for bit 7.