CONDITIONAL BRANCHING ADDITIONAL
I hadn't fully checked that the ACC negative worked, thus I tested this to wrap up the conditional BSC and BSI instructions
The MDX instruction conditional effect needed to be tested for both index register modification as well as the memory work modification variants. I set up values in the registers or memory location and then applied negative, positive and zero modifications to test the skip behavior. The skip should only occur when the modified register or memory location becomes zero or switches signs and that is how it behaved.
MISCELLANEOUS LOAD/STORE INSTRUCTIONS FINISHED
I finished checking with the Store Index (STX). The STX simply stores the value of IAR or the selected index register into the memory at the effective address - displacement from IAR+1 or the second word as an absolute address. .
ARITHMETIC CHECKING
We know that addition and subtraction are essentially working correctly because they are used to create the effective address by every instruction, but there are some aspects that are not part of instruction execution which we should check.
If two numbers are added or subtracted, depending on the result we might set the carry and/or the overflow flags. Numbers in an 1130 word are represented by 15 bits of value and a high order sign bit. Negative numbers are two's complement versions of the positive number. The two's complement of a number inverts every bit and adds 1. Thus the two's complement of 0001 is FFFE+0001 or FFFF.
Whenever the sign bit changes, the Overflow flag is set. This indicates that the 15 bit remainder of the word was not big enough to hold the result. The largest positive number is 32,767 and if a 1 is added to it, the result is now -32768. The 15 bits before the addition were, in hex, 7FFF and after a 1 is added the result is 8000. The sign bit changed and 8000 is -32768.
Whenever their is a carry out of the sign bit (for addition) or a borrow (for subtraction), the Carry flag is set. Shifting left sets the Carry flag to the value of the high bit what was shifted out.
There is an exception for the Shift Left and Count (SLCA) instruction. This shifts the ACC left by a count set in the instruction. If a 1 bit is shifted out before the count gets to zero, Carry is set to 1. If the count dropped to zero, Carry is set to 0.
I had to try various combinations of positive and negative values with addition, subtraction and divide to validate the flags. For shift, I had a smaller number of cases to test. I did try some mixed sign multiply and divide to determine whether the ACC and EXT signs were appropriately generated.
Multiply takes the value in the ACC and multiplies it by the value fetched from the effective address memory location. The result is a doubleword, taking up both the ACC and EXT. This has no effect on the Carry and Overflow flags. The signs came out properly in all cases - e.g. -20 x -40 is the same as 20 x 40.
Divide takes the doubleword value in the ACC + EXT and divides it by the one word value in the effective address location. The ACC stores the Quotient as a 16 bit signed value and the EXT stores the remainder as a 16 bit signed value. The EXT is always the same sign as the divisor (data in the effective address). The Overflow is set if the ACC has an overflow or if the divisor was zero.
When I divided 40,000 which is larger than fits in a single word (but fits in the ACC + EXT as the dividend) by 1, the result was larger than can fit in the ACC thus the O flag was properly set.
XIO INSTRUCTION TESTING
I couldn't more generally test the XIO instructions because many depend on peripheral device controllers. The XIO points at a doubleword effective address which is an Input Output Control Command (IOCC). The IOCC specifies an XIO type, an Area Code to select the particular device, an address and some modifier bits for certain devices.
To determine which device controller(s) are requesting an interrupt, while in the interrupt handling routine, the Sense Interrupt type loads the ACC with the requesting status of all the controllers that can request this particular interrupt level. The bit positions were typically designed by IBM. For example, level 4 assigned bit positions:
- 0 for paper tape reader/punch
- 1 for the console keyboard and printer
- 2 for the 1442 reader/punch
- 3 for the 2501 card reader
- 4 for the 1403 line printer
- 5 for the 1231 optical mark reader
Each device controller typically has its own handler code, so that the interrupt handler, having seen a 1 bit for a particular device controller, then branches to that controller logic to deal with the device. Generally the initial interrupt handler scans the bits using the SLCA instruction, stopping on the first bit from the left that is on, then branches to that device's code.
When the code is done, the interrupt handler exits back to the original code that was running when the interrupt was initiated. A version of the Sense Device instruction will reset the condition that caused the controller logic to request an interrupt.
If more than one controller on the interrupt level had requested an interrupt, the machine immediately goes back to the interrupt handler, which then uses the SLCA to find the next controller with a bit set, branching to its handler code. Only when all requesters have been serviced and their conditions reset will the machine stop entering the interrupt level and continue executing the originally executing program.
The device controller can be interrogated with the Sense Device type of XIO. The controller loads the ACC with a word whose bit positions are defined by that device controller. For example, the console keyboard printer status word assigns bit positions:
- 0 - the typewriter completed a requested function
- 1 - the keyboard had a key pressed
- 2 - the Int Req key was pressed
- 3 -the switch on the console is set to Console (Entry Switches) if on, Keyboard if off
- 4 - the typewriter is busy processing a requested function
- 5 - the typewriter is not ready (either busy or out of paper)
- 6 - the keyboard is busy (KB Sel lamp on)
There are four kind of data transfer types. Read and Write will transfer one word from the address in the IOCC to the device for a write, or save one word from the device in the address for a read. Initiate Read and Initiate Write request the controller to start a transfer of multiple words asynchronously while the CPU moves on and executes instructions after the XIO.
The Initiate types have an address in the IOCC whose first word is a count of words to transfer. The data is transferred to or from the words immediately following the count. For example, to read in a 321 word sector from the disk drive, the IOCC for an Initiate Read points at a 322 word long section of memory, the first word of which contains the value 321.
Finally there is a type that does not transfer to or from memory, called Control. Its modifier and address portions of the IOCC are used by the device controller for its purposes. For example, it may specify a disk cylinder which the drive must reach by moving the disk arm. As another example, it might tell the card reader to steer a card to an alternate stacker pocket.
I have tested the read type and the control type in my code working with the keyboard, using those to read the value of a keypress and to turn on the KB Select status for the keyboard. I have also used a Sense Device to check the state of the keyboard and printer. We know that it resets the keyboard controller request because we exit the interrupt level and resume the main program.
I trie a Sense Interrupt type by triggering an interrupt on IL4 with the Int Req button, single stepping into the interrupt handler and then issuing the XIO to verify that bit 1 is set indicating that the console devices requested the interrupt. That did occur as it should.
Until I have a peripheral device that uses the initiate type of data transfer working, I can't test those two types. A full test of XIO is really tightly tied to testing a particular device and its controller logic. I won't do any further testing at this time.
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