Memory fixed! Beginning general CPU debugging

I WATCHED THE SENSE/INHIBIT WIRES DURING READING, SPOTTED ANOMALY 

After quite a bit of comparative scoping and another round of careful continuity testing, I jacked up the sensitivity on the scope to watch what was seen during the read part of the cycle. I had been seeing the current injected into the wires for inhibiting during the write part of the cycle. That produced spikes of a few volts on the scope with the inputs set to 2V per division sensitivity. 

The same wire is amplified to sense the pulse during the read part of the cycle, but the scope wouldn't see anything at 2V per division. I cranked it down to 20mv per division and hand stepped the machine so that I was only capturing the read action. I should have used a differential probe that was impedance matched to the sense wires, but with the regular probe I just had to contend with a fair bit of noise.

Comparing a working bit with the failing bit 7, it was obvious that I either didn't have the core flipped to a 1 when I wrote to it last, or something was wrong with the sense wire. I popped the ohmmeter on the sense wire contacts and immediately saw that one side of the bit 7 wire had much higher resistance than the others, more than all the properly working sense wires. 

PULLED THE JUMPER BLOCK TO ISOLATE THE WINDINGS AND FOUND THE ROOT CAUSE

I pulled off the jumper block that fits on the backplane so that i could isolate the sense/inhibit wires from the rest of the circuitry. The block fits over a card slot area on the backplane, in the space that normally would have two columns of 12 pins each, D02-D13 and B02-B13. 

The lower half of those columns have drilled holes and the core stack mounted on the other side of the backplane has pins which stick up through those holes. The upper half of the columns have the regular pins inserted and those are connected by traces to the rest of the backplane. 

bottom pins from stack, top on the backplane

Jumper block

Bottom of jumper block

The jumper block connects a pin in the upper half with its assigned counterpart in the lower half. This forms the connection between the backplane and the core stack. With the block removed, the core plane pins are not connected to anything on the backplane.

The block I pulled off connects three sets of sense/inhibit wires, one for the lower 4K of bit 7, one for the upper 4K of bit 7, and one for the lower 4K of bit 9. Each sense/inhibit wire set has three leads. There is a common lead which is connected to ground and two wires, each threaded through 2K of the cores in the bit plane. Five of the six wires had good low resistance to their ground wire, but one had a resistance in the kiloohm range. 

Testing resistance of a sense wire loop

Good wire - low resistance

4.82Kilohms is bad

BROKEN CONNECTION TO THE SENSE WIRES INSIDE THE CORE PLANE

The sense wires, threaded through 2K cores, come out on the top side of the core stack. Three small twisted wires are soldered to each bit plane, one for each 2K wire and one for the common point that ends up hooked to ground. The other end of those wires are soldered to a connection on the base of the core stack, from which they run on traces to the pins that stick through the backplane at the jumper block positions. 

Foam debris on connections

I carefully cleaned a lot of crumbled foam insulation debris from the top and looked carefully. I knew which wires were for bit 7; however no visible fault was detected. My fear was that the wire had broken inside the core plane, which would have been extremely difficult to repair. Another possibility was a broken trace on the base of the core stack or some other connectivity fault. 

Wires connected to baseplate

I hooked the ohmmeter to the pins for the jumper block for the wire set that had the very high resistance. I then very carefully probed on the top of the stack to verify the identify of the working side and the common wire. I then tested the bad connection but it suddenly jumped back to a good connection. 

Connections for bit 7

Frankly, I am not totally comfortable with this because this connection could become loose again. Having not identified the cause nor done something that was a high confidence repair of said fault, I have to be concerned that this can reoccur in the future. Fortunately it is not difficult to get access to the spot where the wire attaches so that it could be corrected again, perhaps more permanently. 

CORE MEMORY WORKING GREAT NOW

I was able to store patterns of all zero and all one throughout memory without parity errors. There may be more tweaking to do in the future but I am relieved that we do not have an unrepairable memory on this system. 

FOUND A COUPLE OF ISSUES WITH INSTRUCTION EXECUTION TO BE REPAIRED

Some instructions when single cycled will bump the Instruction Address Register (next instruction to execute) incorrectly. The IAR should jump by 1 for every short form instruction or by two for a long format instruction, unless we are executing a branch or skip. 

The bump takes place in the first instruction cycle (I1) and the second bump will happen for long format which take the I2 cycle to fetch the second word of the instruction. I noticed that during a execute cycle (E1) it also bumped the IAR, which should only happen with a Modify Index and Skip (MDX) instruction. 

Another instruction that malfunctioned was the Branch and Store IAR instruction (BSI) which is used to call subroutines but also is generated by the hardware to process an interrupt. The instruction stores the IAR in the target address, bumps that address by one, and starts executing code there. Subroutines return by picking up the stored address and branching back to it. 

When the BSI tries to store the address, it gets a parity error. It initially worked okay but then began having this failure mode, both with the injected BSI for interrupt handling and with BSI op codes that I executed from memory. 

Both of these will be easy to track down either with the scope or a logic analyzer. Once I clean these up I will begin a more detailed test of instruction execution, trying all the op codes and all the variations such as indexed, long, indirect etc.