Further testing of CPU instructions 1

CONDITIONAL BRANCHING

There are two kinds of conditional branching, both of which will either execute the next sequential instruction or take an alternate path. In most cases, the alternate path is to skip over one word. The first kind checks against certain conditions that can be tested by the instruction. The second kind skips an instruction when a value becomes zero or changes sign. 

The conditions that can be tested are:

• Accumulator is zero
• Accumulator is negative
• Accumulator is greater than zero
• Accumulator is an even number
• The Carry flag was set
• The Overflow flag was set

The instructions change how they conditionally behave (and whether they do) depending on whether they are short or long format instructions. 

The Branch and Save IAR (BSI) instruction is only conditional when the long format is used; for short format, it will always branch to the effective address + 1 after storing the current IAR in the effective address. 

The Branch or Skip on Condition (BSC) instruction is always conditional, but the use of the condition bits is somewhat different between short and long format. For short format BSC, if any of the selected conditions are true, it skips over the next instruction otherwise it falls through to the next sequential instruction. For long format BSC, if any of the selected conditions are true, the branch is NOT taken and it instead falls through to the next sequential instruction. 

Thus, matching one of the selected conditions will either skip (short) or fall through (long). Inversely, if none of the selected conditions are matched, the short format falls through while the long format takes a branch to the effective address. 

The Modify Index (MDX) instruction acts on the IAR, index registers or a memory location, depending on the format and selection of an index register. 

I tested almost every condition and all the conditional BSI and BSC variants, which all performed correctly. 

A short MDX with no index register will modify the IAR, in other words it is an unconditional branch. It does not skip even if the IAR becomes zero or changes signs, unlike all the other variants of the MDX. Short format uses the last eight bits of the instruction as a displacement, a signed number that is -128 to +127. It is added to the IAR+1 when the MDX is executing, to form the effective address of the branch.

A short MDX with an index register specified will add the displacement to the contents of the index register, putting the updated value back in the register. Thus, you can bump a register up or down by the signed displacement. If the updated value of the register becomes zero or changes sign, then the MDX will skip the next word, otherwise it executes the next instruction. 

A long format MDX with an index register will add the value of the second word to the index register specified. You can bump the register by any value from -32768 to +32767, which is what can be held in the 16 bit word of an 1130. If the updated value of the register becomes zero or changes sign, the MDX will skip the next word otherwise it executes the next sequential address. 

A long format MDX without any index register specified is also called a Modify Memory (MDM). It will add the displacement (-128 to +127) to the contents of the effective address location, storing the new value in that memory location. If the value in the memory location becomes zero or changes sign, the MDX will skip the next word, executing at IAR+2, otherwise it falls through to the next sequential instruction (IAR+1). 

I didn't get to testing the MDX instructions during this session.

MISCELLANEOUS LOAD/STORE INSTRUCTIONS

Load Index (LDX) and Store Index (STX) will act on index registers or the IAR. Unlike an MDX, which takes the current value of the IAR or index register before adding the displacement or second word, the LDX just loads the displacement or second word into the IAR or register, replacing whatever was there. 

If an index register is specified, the displacement or second word (for long format) is put into the index register wiping out its previous contents. 

Updating the IAR is effectively an unconditional branch - either to an address between -128 and +127 if short format is used, or to any address for long format. The STX simply stores the value of IAR or the selected index register into the memory at the effective address - displacement from IAR+1 or the second word as an absolute address. 

Load Status (LDS) and Store Status (STS) transfer the Carry and Overflow tags between the CPU and the memory at the effective address. Bit 14 is Carry, bit 15 is Overflow. When storing status, bits 8 to 13 are set to zero before the Carry and Overflow are used as bits 14 and 15. When loading status, only the bottom two bits are used to set the CPU condition. It is a good practice to put an LDS in the location where the STS will store the status, because then that word can be executed to load the saved status back into the CPU. 

I was able to load the status with LDS and store it with STS. I tested all of the LDX instruction types and they all passed. I did not get to the STX instructions today.