Leaning to use of spare top board connector to bring sense bit 7 signals from core stack to the SLT backplane side

CAREFUL STUDY OF THE UNUSED CABLE CONNECTOR TO FIND FREE PINS

I need three pins for the twisted wire cable from the sense/inhibit winding for bit 7, first 4K words, which is where we have the continuity break between the core stack and the SLT backplane. One of the three is a ground, the other two are sense/inhibit wires for the first 2K and the second 2K of cores. 

The connector I want to use, T-3, runs across the top of the backplane in row 1. It starts partway in column G and ends partway in column K. It is oriented at 90 degrees to the normal SLT card pins. In a card, we have two vertical columns of 12 pins. The top connector has two horizontal rows of 12 pins. 

Just to be confusing, the naming of locations on an SLT backplane has numbers and letters for the major locations, such as where a card is placed. There are eight horizontal rows numbered 1 to 8 from top to bottom. There are eight vertical columns labeled A through N (skipping the letter I, an IBM practice). Rows 2 through 7 are full height and can have an SLT card plugged in to the spot or a connector which uses the same pin layout as a card. 

The top and bottom rows are not full height. They are used exclusively for connectors, never cards. The same pin layout is used for these as for connectors (or cards) in rows 2 to 7, but these are rotated ninety degrees. There are four connector spots at row 1 and another four spots at row 8; these are labeled as T-x and B-x connectors. 

Within each intersection of a row and a column, e.g. E5, IBM also uses letters and numbers for a finer pitch grid. Thus, each intersection has five columns labeled A to E and 14 rows numbered 1 to 14. The pins for an SLT card or connector are placed in columns B and D on this fine grid and are installed only in rows 2 thru 13. Thus, the pins for an SLT card in an intersection are generally labeled D02 to D13 and B02 to B13 using the fine grid names. 

One can therefore have a card at B2 slot, which has a pin B02. The terminology can therefore be confusing unless you mentally switch between the fine grid inside a slot and the gross grid that labels the slots. The reason I had to share this is because of the labeling of the T-1 to T4 slots in row 1 of the gross grid. 

Row 1 and Row 8 are not full height, they don't have fine grid rows 1 through 14 as do the gross grid rows 2 through 7. They do, however, have the very same fine grid columns A through E. I will use the actual pin locations for T-3, the connector location I want to use for my repair, to make this clear.

T-3 is a connector with two horizontal rows of 12 pins. The top row runs across fine grid row 9 and the bottom row runs across fine grid row 11. Thus we need at least 14 fine grid spaces horizontally to fit the pins plus a space, but a gross grid column has only five spaces A through E in it. Therefore T-3 is going to need two full gross grid columns plus a bit of the column before and after it.

For T-3, this means it uses all of H and J gross grid columns, fine grid columns A to E of the first and then A to E of the second. T-3 also uses the last fine grid column, E, of gross grid column G as well as the first fine grid column, A, of gross grid column K. I will use capital letters for gross grid columns and lower case letters for fine grid columns. We know this connector sits in gross grid row 1 so I don't need to repeat that in the list; all numbers therefore are fine grid rows.

The pins of T-3 are, for the top row of 12 pins:

• G e09
• H a09
• H b09
• H c09
• H d09
• H e09
• J a09
• J b09
• J c09
• J d09
• J e09
• K a09

The bottom row of 12 pins are :

• G e11
• H a11
• H b11
• H c11
• H d11
• H e11
• J a11
• J b11
• J c11
• J d11
• J e11
• K a11

Thus when you look at the diagram of the pins used on a backplane, the listings for pins in row 1 and row 8 always look weird. Here is a small sample from the core memory backplane:

Gross grid slot G1 lists four pins, but we now know that the A09 and A11 pins belong to the other connector T-2 and only pins E09 and E11 are part of T3.  In the same way the right end of T-3 sits in gross grid slot K1 but only pins A09 and A11 belong to T-3. The other two are part of connector T-4.

I looked at the backplane listing and saw that three of the pins are not listed, therefore presumably not in use. These are H1 e09, J1 a09 and J1 b09, again using lower case letters for fine grid. Every SLT backplane grounds certain pins. Fine grid d08 pin in rows 2 through 7, all columns. It also grounds pin J1 fine grid a09, something not shown on the backplane listing but key to understand. 

I therefore have just enough open pins to hook up my sense wires for bit 7, 0 to 4095 addresses. The black common wire gets hooked to J1 a09 since it is connected to ground on the backplane when it enters through the jumper block F5. The white and blue wires will be hooked to H1 e09 and J1 b09. 

I will verify this with the ohmmeter and other tests before I begin the installation of a replacement tightly wound three wire cable. I will use a spare SLT card connector from my parts salvage to make the connections to the two pins, so that my cable plugs into T-3 the same way that a cable would have.

ERRONEOUS NUMBERING OF CABLES - VERY DANGEROUS

IBM has a page in the ALDs which shows the cabling required between the SLT compartments. They use the names of the gross grid card slots for connectors that install in row 2-7 columns A, N and sometimes B or M. They use T-1 to T-4 for the top connectors, which should correspond to the official SLT designation of those names. 

This excerpt from the cabling diagram shows the memory compartment on the upper right B-C1 which is used for 4K or 8K sized memory machines using the original 3.6 microsecond core storage. The machine I am restoring is an 8K 3.6us machine so memory is installed there in B-C1.

IBM uses the term Expanded Storage (ES) for machines with more than 8K of memory. An add-on compartment is bolted to the left of the 1130 (called the 'blister' by IBM) and one or two gates are inside with compartments holding core memory. Each compartment holds an 8K core memory, with two compartments per gate and therefore with two gates up to 32K can be configured. 

The red cables in the diagram above area installed only when the machine is bigger than 8K (or with the faster 2.2 us memory but lets ignore that for now). Compartment B-C1 does NOT have core memory inside when the blister is used, but instead has a few SLT cards supporting the extra address bits needed to select above 8K locations. Therefore the signals that come into the B-C1 when it is configured with core memory have to be routed out through A2, A3 and A4 cables to run over to the gates in the blister. 

The additional address bits and control signals for addresses over 8K are connected to B-C1 through connector T-3. If ES is not configured in the machine, then that cable is not installed and T-3 is open. 

The problem is that IBM has labeled this as T2 on the diagram. The signals going into this position over that cable are clearly connected to the pins called T-3 on the backplane listing and the correct name for that position is T-3 according to SLT rules. If they are not using the SLT names for the locations, then they should NOT have used naming like T2 that could be confused, instead using a different naming scheme. 

The pins from gross grid G1 to K1 are part of T-3 as can be seen above. I had to triple check when I found this mismatch. I have claimed in the past that IBM documentation was always accurate, even if it was often unusable or obscure, but this situation disproves that adage.