I checked continuity on many many signal lines. I used the scope to check for the intended signals. All this to figure out why the X current wasn't flowing during a read, but worked okay during writes. Finally as I dug into the circuit behavior and probed around, I realized that one signal was not getting through, the one that enables one side of the current connection for a read operation.
The ultimate cause was an SLT card that was not seated properly in its socket. It wasn't obvious visually as it was only up enough to cause one or more pins to lose contact. When I discovered the card generating the failure and looked really close, I was able to reseat it. Read operations began to work again and I could move forward.
BACK TO CHASING DOWN THE BIT 7 PROBLEM
The symptom is that writing a word with bit 7 set to 1 generates the proper parity but when read back bit 7 appears to be a 0. That causes a parity check. If you write a 0 to bit 7, it does come back as a 0 and thus satisfies parity checking.
I didn't have a lot of time left after I found the loose card but I did perform some testing. It does exclude some potential causes and will help me narrow down the situation to find the root cause.
QUICK REVIEW OF THE PATH OF SIGNALS INVOLVED FOR BIT 7
In the read portion of a memory cycle, the X and Y wires are driven with current in the direction that is defined to flip a core to the zero magnetic orientation. In the midst of that action, a short strobe signal is used to watch for a pulse coming in on the sense/inhibit line that winds its way through all 8K cores in the bit 7 core plane.
If the core had previously been magnetized in the zero direction, nothing happens when we do the read to flip to zero orientation. However, if it had been magnetized in the one direction, the read cycle will reverse the magnetization. This induces a pulse in the wire passing through the cores, which we amplify with the sense amplifier.
That amplified pulse produced when the strobe fires in a ready cycle is routed up through the compartment, over cables to another compartment and down to the B (Storage Data) register card. The pulse, if it arrives, will turn on the flipflop which sets this bit of the register to 1. If no pulse arrives the register remains at 0.
Then when we enter the write part of the memory cycle, the bits from the B register are used to write to the core. The wires from the B register flow over another cable back to the memory compartment and down to the logic cards. They end up driving the inhibit circuit.
When we write to the core memory we are sending the X and Y current in the opposite direction, which flips the core to the orientation we defined as representing a one value. Thus, the read portion sets the bits to 0 and the write portion of the cycle sets the bits to 1. However, we don't always want the core to be at 1, so we need a way to selectively block the flip of the core.
The sense/inhibit wire, which snakes through all the cores on the bit plane, serves this purpose during the write portion of the memory cycle. If we want the core to remain as a 0, we send a current through the sense/inhibit wire in the opposite direction to the X and Y currents. This reduces the magnetic force at the core below the level necessary to overcome its inertia (hysteresis) and flip it.
The B register bits that came back over a cable are gated by a timing signal to be present during the write part of the cycle. The transistors that drive current over the sense/inhibit wire are activated by the emitter strobe during the write cycle, but only conduct if the inhibit signal came through. Thus, with the inhibit signal on, we drive current through the sense/inhibit wire(s) and block the flip of the core to the 1 magnetic orientation. No inhibit signal means we send no current, allowing the X and Y currents to cause the core to flip.
The final aspect that must be mentioned here is that the size of the currents must be carefully controlled. The X current is routed over one of 64 wires, each of which is threaded through 128 cores in each plane. The Y current is routed over one of 128 wires, each of which is threaded through 64 cores, but at right angles to the way the X wires run. Thus, we have 8, 192 cores in the plane but when we run current through an X and a Y wire, we are passing current through 192 cores (64 X and 128 Y).
The current passing down an X or a Y wire is not sufficient to flip a core from one magnetic orientation to another. Thus, 191 of the 192 cores are not changed by the current passing through them. However, the one core that is the intersection of our X and Y wires will receive twice the current, which needs to be over the threshold to cause a flip. We term the memory a coincident current core memory because of this design approach.
The sense/inhibit wire snakes through all the cores, at approximately 45 degrees to the X and Y wire directions. The magnetic core itself is sitting at a 45 degree angle to the X and Y wires also. The inhibit current must be enough to lower the total induced magnetic field below the threshold for a core flip, but not so much that it increases the field at the other 191 cores we are only partially energizing.
3D REALITY IS A BIT MORE COMPLICATED
The core stack is 18 planes, one for each of the 16 data bits and two for parity bits. This the X wire runs through 64 cores on each of the 18 planes, or 1, 152 total cores. The Y runs through 2, 304 cores. Passing current through X and Y causes current in 3,456 cores, but only 18 of them are coincident on both X and Y so only 18 of them have sufficient induced magnetic force to flip them.
The only element that is unique to one bit plane is the sense/inhibit wire(s) for that plane. For engineering reasons, there are four sense/inhibit wires on a plane, each running through 2048 of the cores. These wires work with addresses 0 to 2047, 2048 to 4095, 4096 to 6143 and 6144 to 8191 respectively.
FIRST RESULTS WITH THE SCOPE SHOWS INHIBIT AND SENSE ARE WORKING
I monitored the signals for bit 7 to decide whether we are failing to inhibit or failing to sense properly. I had previously swapped the cards doing the sense and inhibit, but the failure did not move, eliminating the circuitry in those cards. I swapped the B register card for bit 7 with another card, but the error remained so it is not a failure of the B register to latch on the sensed pulse.
I would capture a picture with the CES switch set to write a 1 in to bit 7 and again with the switch set to write a 0 in that bit. I saw that the inhibit signal did turn on when the write was trying to store a 0 in the bit, but not when we wanted a 1 in it. Thus, the signal comes from the B register over the cables and through the inhibit circuitry correctly. I could see an induced current thus we were sending the current through the sense/inhibit wire when we wanted a 0 to be in bit 7.
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| No inhibit, write a 1 |
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| Inhibit, leave core as a 0 |
I think I saw the sense output pulse show up when reading a core that we previously set to a 1, by lack of inhibit, but I have to repeat this to be certain. That is because I was moving the leads between bit 6 and bit 7 to compare a working bit with the failing bit. If I wrote a 1 but the previous time the bit was set to 0, a pulse came out of the sense line. Repeating this again, regardless of what was written in the second half of the memory cycle, did not cause a sense pulse because the prior state of the core was indeed a 1.
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| Sense pulse (purple) flipping core from 1 to 0 during read |
Similarly, if I had written a 0 prior, then regardless of what I was going to write, the sense pulse did not appear. This tracked with the value captured in the B register. If that was indeed what occurs, this is more puzzling as it suggests that we were correctly storing 1 and 0 to bit 7 and correctly reading it back.
If I was confusing the bit 6 results, then when I repeat this testing I might see that the sense pulse is never being detected on bit 7 and that points me in a certain direction. If the sense pulses are being generated in a set of back to back loads, but not when I do a display (read) of the location, the error is somewhere else and more confusing.
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