Believe I have a rework possible on the existing PCB for the loader

DISCOVERED FLAW THAT KEEPS THE CS REQUEST AND OTHER SIGNALS ACTIVE

The design is non-clocked, consistent with the non-clocked design of the IBM 1130. This avoids the requirement to synchronize across clock domains or deal with metastability issues. Four flip-flops establish the state machine for the logic. 

Although these are modern clocked flipflops, the clock is actually the signal from the 1130. For example, when the X6 clock state occurs, the rising edge of that signal becomes the clock to cause one of the flipflops to set its state to 1. A reset signal resets the state machine when a request from the Arduino has been finished - after the state machine raises a 'done' flag, the Arduino drops its request and we reset all the flipflops to the idle state. 

Our first flipflop is set from the rising edge of the Arduino request signal. It then conditions the second flipflop which will be set by the rising edge of the X6 clock state. Each cycle steal is accomplished with eight 450 ns clock states X0 to X7. 

The second flipflop conditioned the third flipflop to be set by the dropping of the CS Level 0 signal from the CPU, which occurs at the end of a cycle steal memory access. The third flipflop conditions the fourth, which is then set when the Arduino request falls. The setting of the fourth flipflop causes a reset of all four flipflops to their idle state. 

When the first flipflop is set I had raised the signals to the 1130 requesting the cycle steal as well as passing along the data and address for the word. Unfortunately, it was not dropped when it should have been. The signal should drop once the second flipflop is activated by the X6 clock state. 

HACK FOUND TO KEEP EXISTING SHIELD WITH MODEST REWORK APPLIED

I had six spare gates on the board, three inverters and three open collector buffers, parts of hex gate chips that weren't fully utilized. I found a way to use two of the open collector buffers to form an AND logic gate since the correct condition for asserting the cycle steal request, address and data is that we have requested a cycle but not yet reached X6. That is, flipflop one is on and flipflop two is off. 

The line to send signals to the 1130 is pulled up to +5 by a new resistor I will add to the board. Two open collector buffer gates are connected to this line as well. If either or both of them pull down the line, it is logic low and we don't assert signals to the 1130. Only when both of the are at logic high do we want signals passed along. 

Thus, one open collector is hooked to the Q output of the first flipflop, so that it does not pull down the common output line if Q is logic high. The other open collector buffer is hooked to the notQ output of the second flipflop, so that it does not pull down the common output line if the second flipflop is not yet set. 

Once the X6 signal arrives and sets the second flipflop, our common output goes low and we have isolated the 1130 from the board. In the idle condition, with the first flipflop inactive, the common output is still pulled low. 

Simplified section of schematic

The simplified extract above shows the use of signals to act as the 'clock' of the flipflops. The green circle shows the new components (actually just using two formerly spare gates). The red circle is where the control line previously ran to drive signals out to the 1130, and the red wire is the replacement connection. 

I will have to cut traces where I applied VCC to the inputs of the unused gates. I will have to cut the line that previously drove the output signals, instead hooking on a pullup resistor to VCC. Finally, I will have to connect the inputs and outputs of the two open collector gates appropriately. 

It is possible that one or more lines that I need to cut are underneath a chip, in which case I have to remove it temporarily to change the traces.