TRACING THE RESET SIGNAL THAT STARTS 1132 LOGIC OUT IN KNOWN STATE
The 1130 has a master reset line that initializes all the stateful parts of the machine. That line is held in reset (logic low) for about 6 or 7 seconds during power up, but it can also be set to logic low when pressing the Reset button on the console.
Since the 1132 has some status that seems illogical involving several latches, one avenue I explored was the possibility that the latches were not initialized properly by the master reset. I traced the net between all the pins that received the master reset signal and discovered that a pin on a card in the B column of the backplane was not connected to the reset nor to the other pins that are fed by the reset.
I resolved this with a wirewrap connection. I remembered that I had found and fixed another trace failure in a card in column B in the last few days. The backplane may have suffered some trauma that caused traces to sever, either the trace itself disrupted by a crack in the glass substrate or a failure of the connection between trace and pin. A crack is more likely if the problems appear localized to the right edge of the backplane as viewed from the wirewrap side, but are in several nets.
I suspect that I will need to develop a full net connection list for this side of the backplane and test out all the connections with a VOM, rather than hoping to find each failed trace through debugging.
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