Preparing for backplane testing after wirewrap repairs

SLOT A2 AND CONNECTOR T1 TESTED FOR CONNECTIONS INTO THE BACKPLANE

The backplane of the 1130 (and S/360) is a four layer PCB made of glass epoxy with circuit patterns photoetched onto each layer. One internal layer provides a ground plane and the other routes power horizontally, with it divided vertically into the horizontal strips for the three power rails. 

The side of the backplane that has pins used with wirewrap is used for horizontal traces. The side where SLT cards plug in has vertical traces. Through plated vias connect the front and back to allow signals to change between horizontal and vertical segments. 

Normally the first and last columns, A and N, are reserved for cables to plug in, as are sideways connectors at the top and bottom which are labeled T-1 to T4 at top and T5 to T8 across the bottom. SLT cards are generally plugged into the columns B through M in vertical rows 2 through 7, although cables can go into B or M. More rarely still, an SLT card could be put into A or N. 

Since our connectivity breaks occurred between B2 and B3, I naturally had tested connectivity for cards C2 and C3. During that testing I verified the connections to A3 as those were routed to cards C2 and C3. I had not tested the slot to the right of B2, namely A2. Nor had I tested connector T-1 which spans across above B2. 

There are no cables plugged into T1 through T4. Wirewrap to those pins was apparently used for debugging by IBM. I also didn't find any any broken connections from A2, A3 or A4. 

CARDS REINSERTED BUT 1130 STAYED IN POWER ON RESET

I put the SLT cards back into the compartment but when I powered up, the system remained in reset mode. Trough a process of trial and error, I found that the problem occurred when card B2 was in the slot. This was the location of extensive wire-wrap repairs I had made, thus this likely was a self inflicted problem.

I began checking all the nets and connections. I found two links that need additional wire-wrap connections and found that the reset input to pin D05 was somehow connected to pin B07, which has an output which keeps the reset signal at logic low. I ran out of time today - got a very late start because I had to accompany contractors into units at our condominium complete which burned up most of the day.