Core memory repaired, operational again

WIRING FROM DIODE ARRAY TO BACKSIDE OF THE BACKPLANE, SLOT J2

I soldered a wire on the top left lead of the diode array for addresses with bits 9 to 11 of 000, routing it up past SLT cards to slot E2 from the rear of the backplane. There, I soldered it onto pin B09 which I had previously checked was unconnected to the rest of the board. 

WIRING ON BACKPLANE FROM SLOT E2 TO CARD IN SLOT G3

The current on the wire will be around 265 ma. I wanted to verify the effect of 30 ga wire, the usual for wirewrap on the backplane. The wire has a resistance of about 0.1 ohms for the length I am using, which produces a voltage drop of .0265 V and consumes 7 mw of power during a read cycle. This is well below its max recommended capacity in a circuit of around 800 ma. 

I therefore wrapped a wire on pin B09 of slot E2 and routed it to connect on pin D10 of slot G3. This completes the circuit path from the Y read drive card to the diode array. Just to be cautious I wrapped a second wire on the same path. 

TESTING RESULTS

The machine was now able to read and write from locations with addresses in that range - of the form xxxx xxxx x000 xxxx (binary) - which used that diode array. I used the Storage Load function to put a pattern of all 0 in core, then used Storage Display function to cycle through the locations. Then I used Storage Load to store a pattern of all 1 bits in core, with Storage Display working perfectly. The last test was to put a pattern of 8001 hex in every location to verify that the parity bit is working for odd parity as well as the even parity of the first two tests. 

The core memory is working again and I can get back to debugging the printer issue and then testing other aspects of the 1130. 

WORRY IN THE BACK OF MY MIND

With several sense wire breaks and now a connectivity break for one of the read drive lines, I have to worry that there is some condition on the core stack that might lead to further breaks on that bottom board. At some point I will run out of unassigned pins on the backplane and the task of routing extra wires will become too cumbersome. Plus, when the machine is trucked back to its home in New Jersey, the vibration and jostling might well induce further failures if the core stack is 'on the edge'. 

I therefore did some preliminary design thinking about a replacement for the core stack. Rather than using the SLT cards and wiring inside the compartment, I would just intercept the four control signals (select, use, read and write), plus the address, the incoming data word and the outgoing sense bits. 

Nonvolatile SRAM is much faster than the core memory access times, allowing easy engineering of a substitute with a relatively simple state machine to drive its response to CPU core access requests. I found a part, for example, which provides the 8K words plus parity in a single chip for about $12. It uses a lithium battery to preserve contents while powered off, with a life of at least 10 years. 

Therefore if the worst happens, I can disconnect power to the core stack, insert a small board into the compartment with the nonvolatile RAM, and have the machine operate exactly as it would have with the core installed. The one capability that would be lost is the ability to play songs over an AM radio near the core stack.