I was taking traces using the scope and sporadically executing a XIO Sense DSW command to see the status returned by the controller. Out of the blue, when I pushed the Prog Start to try another sense command, the Parity Stop struck. It seemed to be a hard error.
CHECKING SIGNALS AND VOLTAGES ON STORAGE
I verified all the important voltages on the memory backplane and then monitored the memory signals with the scope. Most looked fine, until I checked the Y read drive current which was not present during the read half of the memory cycle.
SPENT A BIT OF TIME TESTING ADDRESS BITS TO THE Y READ DRIVE CARDS
One possibility that could produce this error is when the gate driving read current to a block of diodes on the core stack, responsible for a range of memory locations, does not activate because one or more of the addressing bits are wrong or missing. I quickly eliminated that possibility.
FAIRLY EXHAUSTIVE TEST OF ADDRESS RANGES TO NARROW DOWN THE FAILURE
Still suspecting that the issue was a failure of the Y read drive and Y read gate current, but seeing the current flow correctly for writes, I realized it would likely be one or more cards rather than all reads. To pinpoint the card involved, I began varying the address from which I tried to read memory contents.
ADDRESSING 101
The addressing for core memory uses bits 9 to 11 for the high side of the Y address. This selects one group of 16 wires in the Y axis. Using bits 12 to 15 to select which of the 16 lines in each group will be active allows the selection of one of the 128 wires running through core in the Y axis.
Bits 3 to 5 select the high side of the X address, picking one group of 8 wires for the X direction. Then, bits 6 to 8 select which of the 8 lines in each group will be active. This picks one of 64 wires running in the X axis.
CHECKING ALL Y ADDRESSES WITH X HELD STEADY AT 000000
I set bits 3 to 8 to all zero, then varied the lower address bits to see which ranges worked and which had parity errors because the cores were not flipped. Starting at 000 0000 repeated the solid parity checks, but when I set the upper three bits to any non-zero value, all sixteen locations selected by the bottom four bits worked well. In other words, for bits 9-11 at 001, 010, 011, 100, 101, 110 and 111, all sixteen values for bits 12-15 read perfectly. It was only when 9 to 11 were set to 000 that I had solid failures and they were all in sixteen values of bits 12 to 15.
CHECKED ALL X ADDRESSES WITH Y HELD STEADY AT 0010000
I had a suspicion that I knew the failure already but for completeness sake I varied all the upper bits 3 to 7 just in case there were addressing problems with the X lines also. Every value from 000 000 to 111 111 worked just fine.
MEMORY ADDRESSING 101 CONTINUED
The current was flowing fine on the write half of the memory cycle, which means that the Y wires were intact running through the core stack. Further, reading and writing use the same wires but alternate the flow of current such that the read flips a core to the 0 magnetic direction and a write will flip the core to a 1 magnetic direction until the inhibit wire current in on to block the flip.
Each high part of an address, X or Y, is connected to the common side of a diode array. Diodes oriented in one direction (of current flow) are connected to the 8 or 16 wires in a group. Diodes oriented in the opposite direction are also connected to the same 8 or 16 wires.
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| rotated 90 degrees left in real life |
Focusing specifically on the Y axis since that is where we have the failure, the diode arrays have 16 connections. Physically there are two arrays of 8 connected to the same common point. That common point is fed by the read driver/write gate card for the particular value of address bits 9 to 11 that are wired to the common point. Since we have eight combinations of bits 9 to 11, there are eight wires connected to eight pairs of diode arrays, one for each address combination.
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| Diagram of diode arrays associated to address bits |
RECOGNIZING AND VERIFYING THE FAILURE
The write gate side of the diode array worked just fine for bit 9-11 of 000, but the read driver side did not. The path of the read driver signal for Y high bits 000 comes out of the G3 card at pin D10 and is routed to a jumper block at D5. There, the signal is passed to pins on the core stack, routed through the bottom PCB board of the stack and then discrete jumper wires carry the signals from the bottom board to the top board where the diode arrays are mounted.
The signal for reader drive high bits of 000 goes to the very outermost clip on the bottom and top board, which may be why it was at risk. However, I don't see any damage there. More likely this is yet another failure of a trace on the core stack bottom board, where we previously experienced three sense wire trace failures.
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| Diode board on top of core memory stack |
I verified this by first proving connectivity from G3 B08, for bit 9-11 value of 001, to the second set of diode arrays on the board. Then I checked for G3 D10 to the first set of arrays, where of course we found a nearly open circuit.
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| Jumpers from bottom board to diode board |
PLANNED REPAIR TO BE EXECUTED ON NEXT VISIT TO THE SHOP
The fix will be similar to how I repaired the sense wire breaks. I will solder a wire to the diode array, route it to the backside of card slot J2 which is unpopulated on the IBM 1130. Two pins are unused and not connected to any traces - D02 and D11. For convenience of access I will use pin D11. Then on the backplane side I can run a wire between J2 D11 and G3 D10 restoring connectivity.
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| Red circle around diode lead to attach wire |
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| J2 slot with red circles on pins D02, D11 |
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